module spi_slave_wrapper_test_bench();

reg clock, resetn, read, write, chip_select;
reg [7:0] writedata;
reg [2:0] address;
wire spi_miso;

wire [7:0] readdata;
wire wait_request;
wire spi_clk, spi_mosi, spi_cs;

spi_slave_wrapper DUT
(
        clock,
        resetn,
        writedata,
        read,
        write,
        chip_select,
        address,

        readdata,
        wait_request,

        spi_clk,
	spi_cs,
        spi_miso,
        spi_mosi
);

initial
begin

	// initialize
        clock = 1'b1;
        resetn = 1'b1;
        writedata = 8'b0;
        read = 1'b0;
        write = 1'b0;
        chip_select = 1'b0;
        address = 3'b0;

        @(posedge clock)
        resetn = 1'b0;
        @(posedge clock)
        @(posedge clock)
        resetn = 1'b1;

	@(posedge clock)
	writedata = 8'haa;
	chip_select = 1'b1;
	write = 1'b1;
	address = 3'd2;

	@(posedge clock)
	writedata = 8'hbb;
	chip_select = 1'b1;
	write = 1'b1;
	address = 3'd2;

	@(posedge clock)
	writedata = 8'h02;
	chip_select = 1'b1;
	write = 1'b1;
	address = 3'd1;
	@(posedge clock)
	writedata = 8'h00;
	chip_select = 1'b1;
	write = 1'b1;
	address = 3'd0;
	@(negedge wait_request)
	@(posedge clock)
	writedata = 8'h00;
	chip_select = 1'b0;
	write = 1'b0;
	address = 3'd0;
	@(posedge clock)
	chip_select = 1'b1;
	read = 1'b1;
	@(posedge clock)
	chip_select = 1'b0;
	read = 1'b0;
	@(posedge clock)
	chip_select = 1'b1;
	read = 1'b1;
	@(posedge clock)
	chip_select = 1'b0;
	read = 1'b0;

end



assign        spi_miso=spi_mosi;

always
        #10 clock = ~clock;
endmodule

